High-Level Power Analysis and Optimization

Designers often find the biggest gains in energy use at the architecture and behavioral levels of a chip's design hierarchy, and this book focuses there. It explains how to estimate and reduce power consumption during behavioral synthesis and for designs written at the register-transfer or architecture level.

The text reviews current research in three areas: power estimation through macromodeling for architecture-level designs, techniques for managing power at the high level, and synthesis optimizations aimed at low power consumption.

It is intended for students, researchers, working designers, developers of design methodologies, and builders of electronic design automation tools who work on low-power VLSI or high-level design methods.